BIOS Modification - DFI 586IPVG, Cyrix MII 433, K6-2/+ 450

[KachiWachi]

Hey all --

I've posted this before in the old forum and over at th's PCChips forum, but haven't had much progress/help since then, so I thought I'd repost it here again in the Advanced Section.

I'm looking to read the CPU Tables in my BIOS to see just what it knows about each one it supports in an attempt to add support for my current one. From the old post and what I have learned since, I won't have to add anything serious, just let it know that mine exists so that it doesn't default to an unknown and hang the board.

Current CPU is a Cyrix MIIv 433GP (3x100). My BIOS shows it as a 6x86L but I can only run it at 3.5x66. Would like to run it at 4.5x66, but the BIOS seemingly won't allow that, even though the chipset registers do not change for the L/MII series (so I've been told). The board does support BF2, but I've never had anything that uses that installed before. The processor was brand new when purchased, so I can only assume it is functional. Motherboard is a DFI 586ipvg Rev. AD+ (all info, manual (.pdf), and BIOS can be found at DFI website).

So all I want to do is add an identification line to the BIOS that says...here is where to go and what to do when you see this...simple as that.

Is there a utility out there that can do this easily, or am I in for a battle?

Thanks for your input.

[KachiWachi]

Just keeping this alive... No help from the FORUM EXPERTS here on this??

[Rainbow]

Don't know about CPU tables, I do fixes over 32GB

[KachiWachi]

Thanks Rainbow for replying.

There has got to be some sort of utility that can look at this...I mean if you can add Large HD support, why can't you add CPU support, especially in my case where I don't need to add register settings, etc... just tell it that this combination exists in this world. The BIOS already has support for multipliers using BF2 for AMD CPU's, so this should be cake.

Anyone else???

[Rainbow]

Everything is undocumented in BIOSes because it's Award own code...
Petr Soucek did the first 32GB fix and CPU table modification I have seen.

[KachiWachi]

Does the same go for AMI?

How then to these BIOS Upgrade companies do it??

[Rainbow]

I think that Unicore has access to Award BIOS source code, so it should be easy for them.

[Denniss]

Is it possible to extract an INT13 Module from a newer AMI-Bios(K7S5A as example) and insert this module in an older Bios( Pcchips M560 or others) to give them support for HDD up to 128GB ?
As far as I know this Int13 modules handles the IDE drives and detection .

[Rainbow]

Haven't tried that - I don't have such large drive

[Denniss]

Look at this site :
http://web.inter.nl.net/hcc/J.Steunebrink/k6plus.htm
This guy is modifying CPU-tables for K6-2+ support .
Maybe he can tell you how to do it for your Cyrix M-II .

[KachiWachi]

Just heard from Jan Steunebrink so I thought I'd bring you all up to date.


"Oke, I disassembled the BIOS and found the Cyrix ID lookup table.
It doesn't go any further than 54h / 5Ch (3.5x), and the Cyrix detection
algorithm is such that when it sees 55h / 5Dh it doesn't even recognise the
CPU as a Cyrix and it messes up the initialization completely!
So Peter Missel was right on this one.

I did a quick patch to test if the 4.0x mode wil work. The Cyrix ID table
uses 4 bytes for each entry. The first 2 bytes contain the DIR0 ID bytes,
the 3rd byte indicates the CPU type for the BIOS and the 4th byte the CPU
features.
At the beginning of the Cyrix ID table there was an 21h / 23h ID entry for
an early model 6x86. I've replaced this entry with the 55h / 5Dh ID bytes
for the MII in 4.0x mode and also adjusted the CPU features byte to match.
In addition I've changed the FSB byte in the CPU speed table for the 300MHz
entry from 60 to 66/75MHz. This will ensure a correct Auto configuration of
the chipset registers when you are able to run the CPU at 4.0x75MHz.

I've checked several other Cyrix init subroutines and I believe it should
work with the above changes.
Attached is a (zipped) copy of the patched BIOS. The filename is
2A59GD4J.BIN and you can flash it with the program you normally use the
flash a BIOS on this board.
Please let me know if this works, and what the BIOS indicates for CPU type
and speed on the boot and summary screens now, when you set it to 4.0x66.

Greetings,
Jan."


So I'm going to try this over the weekend...wish me luck!!

[KachiWachi]

SUCCESS!!!

Jan's patched BIOS file loaded with no problems, and it came up as before in 3.5x66MHz. Things seemed OK, so I opened the box and set it for x4. Machine booted as 6x86MXL @266MHz and continued on thru the POST.

A quick test using WinTune98 shows:

Cyrix 6x86
(1) 232 MHz
Windows 98 4.10.2222 A
Diamond Stealth 3D 2000 (S3 ViRGE 325)
800x600@24bits/pixel
557±0.8(0.14%) MIPS (Integer operations)
185±0.11(0.058%) MFLOPS (Floating point operations)
41±0.012(0.03%) (Integer application simulation)
22±0.23(1%) (Floating point application simulation)
37±0.043(0.12%) (MMX application simulation)

CPU Details

CPU load: 1
low MIPS: 500
CPUID: 0x0601 0x80A135
MMX Present: True
3DNow Present: False
dhrystone time (s): 3.6
whetstone time (s): 0.054
Integer time (s): 19
Floating point time (s): 31
MMX time (s): 25

And now ---

Cyrix 6x86
(1) 266 MHz
Windows 98 4.10.2222 A
Diamond Stealth 3D 2000 (S3 ViRGE 325)
800x600@24bits/pixel
627±0.11(0.017%) MIPS (Integer operations)
212±0.48(0.22%) MFLOPS (Floating point operations)
45±0.075(0.17%) (Integer application simulation)
25±0.25(0.97%) (Floating point application simulation)
41±0.053(0.13%) (MMX application simulation)

CPU Details

CPU load: 3
low MIPS: -1
CPUID: 0x0601 0x80A135
MMX Present: True
3DNow Present: False
dhrystone time (s): 3.2
whetstone time (s): 0.047
Integer time (s): 17
Floating point time (s): 27
MMX time (s): 22

Not sure what the CPU LOAD and low MIPS is doing but...looks like about a 13% increase overall. (Any help on that??)

YIPPIEE!!!!

Now......

Jan says that 4.5x is not documented in the Cyrix literature that he could find. So *Experts*...do we think this could work, or is it a crapshoot? I would need to ask Jan to patch this in so please post your input. Right now though I'm gonna see what this guy can do now.

[KachiWachi]

Here is some info on what else my system has for your comment on if I will be able to run this guy *safely* at 75MHz.

I have a i430VX chipset (of course), Good 60nS EDO RAM (128MB), a Diamond Stealth 3D 2000 Video card, an Adaptec AIC-7850 SCSI Card (with a Yamaha CD Writer and ZIP-100 attached), USR 56K ISA FaxModem (not WinModem), an Aztech SC-16 3D ISA Sound card, a WD AC2850 and a Maxtor 7540AV Hard Drive setup...both are MODE3 and MW-DMA1 capable only and are 900 and 500 MB capacity. (Remember also, I got most of this for free from work so...)

Peter Missel had mentioned something about the L2 Cache not being able to handle the increase... I have what appear to be 75 MHz capable chips there (RAM is marked -75 and the TAG is -12) but I will check into that to be sure so...and with the age of the drives he was saying also they may be suspect (as there is no error correction going on so)...

L2 Cache Chips verified to be 75MHz compliant... MoSys MCache series MC80164K32Q-75 PBSRAM... -75 for 75MHz operation, 3-1-1-1 Burst Read, 3-1-1-1 Burst Write, 3-1-1-1-1-1-1... Pipeline Operation. So they look good to go for 75MHz...

The -12 in the TAG is for 12ns so 1/12nS=83.33MHz, so no problem there either.

As for the IDE interface, I know is controlled by my VX chipset (South Bridge I just learned), but are the Driver Chips part of that IC? If they are seperate, what might some common part numbers be??

[Rainbow]

I think that all Pentium chipsets from Intel are officially 66MHz only (Pentium CPUs have only 50/60/66MHz external clock) but many boards provide 75MHz or 83MHz settings.

[KachiWachi]

Just tried Patch #2 from Jan to try 4.5 and 5x modes...

No joy here...it wouldn't take the jump to lightspeed.

It stayed the same at 266MHz, and ChkCPU showed the same data as before. I only tried 4.5x...never planned to go higher anyway, so I assume 5x is broke as well.

Thing is, I assumed it would have worked as the CPU reacted to that jumper previously. I don't know how it is wired inside, but I would have thought that since you need the middle jumper for 3x mode (which it was running at before we started this) that it would have continued on up the truth table... The Cyrix App Note 119, page 21 shows a table up to 5x, but I don't know if it is an actual spec or just a reference table... Is there any way to find out for sure?

Anyone know how a CPU Multiplier actually works??